1. Field of the Invention
The present invention relates to a digital-to-analog converter used for audio systems and various communicating equipment, and more particularly to, a switched capacitor digital-to-analog (hereinafter simply referred to as "D/A") converter for effectively decreasing harmonic distortion and shrinking the designing area by means of analog switches and capacitors, in a data converter using a digital 1-bit data stream as an input and an analog signal as an output.
2. Description of the Prior Art
D/A converters generally function to convert a signal received in a digital state into a signal in an analog state. Preferably, such a D/A converter is operated within a linear input range and has a larger dynamic range.
Currently, the most widely used method is to increase the dynamic range while heightening resolution in low frequency signals below 100 KHz, i.e., an oversampling technique using a delta-sigma system.
In considering the conventional D/A converter having the above-stated characteristics, a circuit as shown in FIG. 1 may be given as one example, especially, the D/A converter having the formation as shown in FIG. 1 is called as a switched capacitor 1-bit D/A converter.
The circuit includes a D/A converter section 40 formed by a first signal input section 10 consisting of a plurality of analog switches DSW1d, /DSW1d, SW1, SW2 and SW2d and capacitors C1 for receiving a digital 1-bit data stream, and first and second resistor sections 20 having bypass capacitors C.sub.B for decreasing high frequency components of a signal received via first signal input section 10 to lead a first fully-differential operational amplifier 30 to operate within a linear input range and a plurality of analog switches SW1, SW1d, SW2 and SW2d for attenuating the high frequency components of a value provided from first fully-differential operational amplifier 30. First fully-differential operational amplifier 30 performs an arithmetic operation of signals received via aforementioned respective sections to amplify them. Also included as a part of the circuit is a switched capacitor low-pass filter 50 which uses the signal supplied from first fully-differential operational amplifier 30 as an input to eliminate a high frequency noise.
Switched capacitor low-pass filter 50 illustrated in detail in FIG. 2 includes a second signal input section 51 formed by a plurality of analog switches SW1, SW1d, SW2 and SW2d and capacitors C3 for receiving the signal supplied from first fully-differential operational amplifier 30. In addition, a second fully-differential operational amplifier 52 is amplified to provide the signal received via second signal input section 51, and third and fourth resistor sections 53 are provided for removing the high frequency noise produced when a voltage is transmitted from second signal input section 51 to second fully-differential operational amplifier 52.
Here, analog switches SW1 and SW2 within second signal input section 51, analog switches SW1d and SW2d within third and fourth resistor sections 53 and capacitors C4 serve as the low-pass filter having a cutoff frequency of ##EQU1## (where reference alphabet f denotes a clock frequency shown in FIG. 3) together with capacitors C5 connected between the input and output terminals of second fully-differential operational amplifier 52.
The operation of the switched capacitor D/A converter as constructed above will be described.
Among the reference symbols in connection with the switches illustrated, a difference between the reference symbols SWn (n=1,2) and SWnd (n=1,2) is that switch SWnd is operated by delaying a predetermined time period after switch SWn is operated in accordance with the timing chart as shown in FIG. 3.
That is, the timing chart of FIG. 3 represents one example of a phase for rendering respective analog switches SW1, SW1d, SW2 and SW2d to be on or off.
Respective analog switches are formed of MOS transistors as shown in FIG. 3.
In association with the operation in D/A converter section 40, when switches SW1d are on after turning on switches SW1, both ends of capacitors C1 of first signal input section 10 are respectively charged with a voltage of V.sub.ref+ -0 (voltage at both ends of the upper capacitor) and a voltage of V.sub.ref- -0 (voltage at both ends of the lower capacitor) if the digital 1-bit data stream D is high while being charged with voltage of V.sub.ref- -0 (that is at both ends of the lower capacitor) and voltage of V.sub.ref+ -0 (that is at both ends of the upper capacitor) if the digital 1-bit data stream D is low. Also, the voltages at both ends of capacitors C.sub.R of first and second resistor sections 20 becomes zero.
At this time, switches SW2 and SW2d connected between capacitors C1 of first signal input section 10 and capacitors C.sub.R of first and second resistors 20 are in the off state.
When switches SW2 and then switch SW2d are on after switch SW1d is off in accordance with the phase of the input clock for controlling operation of overall switches upon the completion of the charging operation, the voltage charging up capacitor C1 of first signal input section 10 is applied to the input terminals - and + of first fully-differential operational amplifier 30. Additionally, since one side of capacitors C.sub.R of first and second resistor sections 20 are connected to output terminals + and - of first fully-differential operational amplifier 30, the charged voltage becomes discharged to capacitors C.sub.R of first and second resistor sections 20. At this time, the magnitude of a switching noise ocurring at a moment (an interval of the clock transiting from low to high) that the switches are to be on in accordance with the size of switches SW1, the rising and falling edges of the clock, the time of a non-overlapping clock and the size of capacitors C1. This noise is imposed upon the input of first fully-differential operational amplifier 30, so that the output signal is instantaneously deviated from a linear range. For this reason, a distorted signal is produced to decrease the dynamic range.
In order to prevent this incident, bypass capacitors C.sub.B are connected between both ends of input terminals of first fully-differential operational amplifier 30 to decrease the magnitude of the voltage switching noise by an RC.sub.B time constant (where R denotes a resistance value of switch SW2). Then, the output involves the signal operated with the linear range to enhance the dynamic range. Here, first fully-differential operational amplifier 30 is operated as the low-pass filter having a cutoff frequency of ##EQU2## by feedback capacitors C2 of first fully-differential operational amplifier 30 and capacitors C.sub.R of first and second resistor sections 20, thereby eliminating the high frequency components.
The output voltage of first fully-differential operational amplifier 30 of which high frequency components are eliminated is supplied to switched capacitor low-pass filter 50.
In describing the operation of switched capacitor low-pass filter 50, respective switches are operated in accordance with the clock phase shown in FIG. 3 as in the description with reference to FIG. 1, and this clock is applied to gates of the switches to turn on or off respective switches.
As shown in FIG. 2 in switched capacitor low-pass filter 50 operated with the same principle as D/A converter section 40 of FIG. 1, when switches SW1d are on after switches SW1 are on the output voltage of first fully-differential operational amplifier 30 charges respective capacitors C3 of second signal input section 51. Also, the voltages of both ends of capacitors C2 of third and fourth resistor sections 53 are discharged to be zero.
After switches SW1d are off in accordance with the phase of the input clock (refer to FIG. 3) for controlling the operation of overall switches upon completing the charging prior to turning on switches SW2 and then switches SW2d, the voltages charging up capacitors C3 of second signal input section 51 are applied to input terminals - and + of second fully-differential operational amplifier 52. Since one sides of capacitors C4 of third and fourth resistors 53 are connected to output terminals + and - of capacitors C4 of third and fourth resistors 53, the charging voltage is discharged to capacitors C4 of third and fourth resistors 53. Consequently, switched capacitor low-pass filter 50 functions as the low-pass filter having a cutoff frequency of ##EQU3## by feedback capacitors C5 as in D/A converter section 40 of FIG. 1.
In order to prevent the appearance of distortion at the output of the operational amplifiers resulting from the switching noise of the high frequency components produced from the input terminals of the operational amplifiers as described hereinbefore, conventional D/A converter operated as described above adopts a method for connecting the capacitors (bypass capacitor) to the input terminals of the operational amplifier to make the output of the operational amplifier operate within the linear range.
Therefore, the larger the value of bypass capacitors C.sub.B is (i.e., the value of C.sub.B which satisfies the relation that RC.sub.B time constant is less than {1/2.times.clock frequency!}), the increased linear range of the fully-differential operational amplifier is obtained. Thus, total harmonic distortion is decreased and the dynamic range is increased.
As one example, at Phillips Co., Ltd., a chip is currently being designed by using a large capacitor such as 85 pF to 16-bit audio D/A converter.
However, if the capacitance of the capacitor is increased as above, the capacitor cannot be provided in the interior of the chip in its design. For this reason, it is designed to connect the bypass capacitor to the outside of the chip in the D/A converter.
Such a construction is unfavorable for current products directed toward achieving high miniaturization due to occupying too wide an area. In contrast, when the capacitance of bypass capacitor C.sub.B is small, the dynamic range is decreased.